In general, as the degree of integration in semiconductor devices advances, the design rule of the semiconductor device is decreased or miniaturized. As the miniaturization of the design rule rapidly proceeds, the size of a source/drain and the line width of a gate electrode and a metal interconnect decrease in a MOS transistor. Several methods are provided to fabricate a semiconductor having a fine line width. A chemical mechanical polishing (hereinafter referred to as “CMP”) process is one of the methods. The CMP process planarizes a layer of a substrate using both a mechanical strength and chemical interaction caused by slurries. The CMP process can polish a layer of a substrate to a precise thickness and uniformly planarizes the whole area of the substrate. Thus, the CMP process is the essential step in a recent process for fabricating a semiconductor device having a fine line width.
In detail, the CMP process comprises the following steps. First, the CMP process is performed in an apparatus such as the example CMP apparatus of FIG. 1. Referring to FIG. 1, the CMP apparatus includes a carrier head 105 for fixing a substrate through absorption. A carrier film 106 is adhered to the bottom portion of the carrier head 105. Thus, the substrate can be held by the carrier film 106. A rotating platen 101 is placed away from the bottom portion of the carrier head at a predetermined distance. A polishing pad 102 is installed on the upper portion of the rotating platen 101. A slurry injection nozzle (not shown) is positioned away from the upper portion of the rotating platen 101 at a predetermined distance. Here, the slurry nozzle supplies slurries during polishing. A pad conditioner 104 apart from the carrier head 105 is installed on the predetermined portion over the polishing pad.
Upon the starting of the polishing process, the rotating platen 101 begins to spin. Next, the carrier head 105 may move downward until the polishing pad 102 on the rotating platen 101 contacts with the substrate 103 adhered to the carrier film 106. After the substrate contacts with the polishing pad, a self-rotation movement and a horizontal fluctuation movement are carried out by a predetermined device (not shown). While the self-rotation movement and the horizontal fluctuation movement are carried out, slurry is blown from the slurry injection nozzle. The blown slurry is then supplied to the polishing pad. Therefore, a mechanical polishing is performed along with a chemical polishing, which is caused by a chemical reaction between the slurry and the pattern of the thin layer of the substrate 103. After the CMP process is performed, the pattern of thin layer deposited over the substrate is polished to a predetermined thickness and the planarization completed. Meanwhile, a policy for determining the polishing endpoint of a polishing target such as the pattern of the thin layer should be provided for the CMP process. A desired semiconductor device can be then fabricated by predicting the polishing endpoint and performing the CMP process to the endpoint.
FIG. 2 illustrates, in a cross-sectional view, an embodiment of the process for fabricating a semiconductor device according to the prior art. Referring to FIG. 2, a first metal interconnect 202 is formed on a substrate 201. An interlayer dielectric layer 203 having a via hole is formed on the first metal layer. Here, the via hole is formed to be in contact with the first metal layer 202. Next, a predetermined metal layer such as a tungsten layer is deposited over the whole area including the via hole to make a plug. Here, the plug is an electric device to connect the first metal layer and a second metal layer which will be deposited through a later process. Next, the plug is then made by the planarization of the tungsten layer through the CMP process. Here, a polishing endpoint is the surface of the interlayer dielectric layer during the CMP process for the tungsten layer.
At present, two methods are largely used to detect the polishing endpoint. One method is an end point detection (hereinafter referred to as “EPD”) method that uses the material characteristics between the polishing target and the layer under the polishing target. The second method is to measure the polishing thickness by manipulating a polishing speed calculated based on the inherent polishing degree of the polishing target material.
According to the first method, a predetermined gas is blown to the polishing area during the CMP process to determine whether the bottom layer of the target such as an etch stop layer is detected or not. If the etch stop layer is detected, the CMP process should be stopped. However, because the CMP process is stopped only after the etch-stop layer is detected, the unwanted thickness of the etch stop layer is inevitably polished.
The second method is prevalently adopted for the present CMP process. The second method can calculate the accurate polishing speed for the polishing target by using the characteristics of the CMP apparatus such as the rotation speed of the CMP apparatus and the polishing degree of each material. Therefore, the polished thickness is determined on the basis of the polishing speed.
However, the polishing amount of the target can deviate from the required thickness due to the state of the material or the CMP apparatus. The characteristics of the semiconductor device may be deteriorated. Thus, after the CMP process is completed, the polishing degree of the target should be measured.
At present, two methods are provided to measure the polishing degree after the completion of the CMP process. First, an operator visually confirms the polishing degree with a microscope. A second method is to move the polished substrate to a resistance measurement apparatus to determine the accuracy of the polished thickness.
According to the conventional method, the resistance measurement apparatus apart from the CMP apparatus or the bare eye inspection of the operator is used to confirm whether the polishing target has been accurately planarized to a predetermined endpoint or not. However, according to the resistance measurement apparatus, the yield of a semiconductor device may decrease due to the movement step of the polished substrate to the resistance measurement apparatus. Moreover, the visual check cannot guarantee reproducibility and accuracy.
U.S. Pat. No. 6,547,637 to Zhang et al., discloses a device and method for detecting endpoints of a chemical-mechanical polishing process for semiconductor wafers. U.S. Pat. No. 6,537,133 to Birang et al. discloses an apparatus and method of chemical mechanical polishing (CMP) of a wafer employing a device for determining, in-situ, during the CMP process, an endpoint where the process is to be terminated. U.S. Pat. No. 6,514,775 to Chen et al. discloses in-situ techniques for determining process end points in semiconductor wafer polishing processes. U.S. Pat. No. 6,293,845 to Clark-Phelps et al. discloses a method and system for detecting a planarization endpoint of a semiconductor wafer planarization operation, which includes monitoring a motor current, a carousel motor and a head motor. U.S. Pat. No. 6,191,846 to Opsal et al. discloses an apparatus for characterizing multilayer samples comprising an intensity modulated pump beam and a probe beam.